JTAG using USBee SX
JTAG (Joint Test Action Group) is a standard commonly used for debugging circuit boards and embedded systems.
All kinds of interesting things are possible. For embedded microcontrollers it allows reading and writing memory, re-flashing, single stepping, and other vendor-dependent operations. It also makes so-called "boundary scan" possible, overriding the physical input and output pins of the chip to test other devices connected to it. Multiple integrated circuits on a board connected in a so-called JTAG chain. This allows them all to be tested using one physical access port. This page by Mark Whitis gives an excellent description of JTAG and how it works...
In addition to the (expensive) JTAG equipment for sale by the chip vendors themselves, there are several JTAG cables for sale, most of them connect to the parallel port, some newer ones connect to USB. It is also pretty doable (with a little electronics knowledge) to built one yourself. But instead of buying or building yet another cable, I want to reprogram the USBee SX logic analyzer for it. The flying leads can be used to connect to different JTAG connectors without having a bunch of adapters.
In my PWM project I built a custom firmware that programs the I/O pins of the USBee SX. Also, there appear to be a few open source projects already around that Cypress FX2 into a JTAG adapter. It looks like this is a matter of changing the I/O ports to match the pinout.
- ixo-jtag This firmware allows a USB-capable microcontroller - currently that's primarily the Cypress FX2 EZ-USB family, or an FTDI FT245 in combination with a CPLD - to act like an Altera USB-Blaster JTAG pod)
- Xilinx USB JTAG (JTAG interface using Cypress EZ-USB, bit banging)
- UrJTAG: Universal JTAG library, supports the Xilinx and ixo-jtag cables
The first two provide s a firmware, which is not entirely right for our case (as only PORTB is connected to the output), but it can be adapted.
I have made an adapted version of ixo-jtag firmware for the USBee. The biggest problem was that 'renumeration' does not work for some reason, and I thus had to remove all USB Blaster compatibility. This is not a big loss for me, as except for off-the-shelf software compatibilty there is no need to emulate a FTDI chip at all. This means that changes to UrJTAG will be required.
To be able to test it I made some Python diagnostic tests and a port of the HairyDairyMaid WRT54GL "debrick" tool to my interface, and attached it to the JTAG header on the Belkin F5L049 board in the following way:
TAP Reset signal
nTRST is a "TAP Reset" signal and its active level is "0" (the first "n" indicates negative logic). This signal resets TAP controller independently from the CPU logic. To conform to MIPS EJTAG specifications this pin is pulled to the ground via resistor ~1KOhm to keep TAP in reset state without probe attached. If probe is controlling the device, you need to feed logical "1" to
nTRST pin or pull this to the +VCC via ~300Ohm resistor. I wired Output Enable (OE) to this pin. This is really important, otherwise JTAG will not work. Initially forgot this and it was in "pretend-dead" mode.